This invention generally relates to semiconductor processing and more particularly solder bump formation in flip chip bonding technology and a method for protecting an uppermost passivation layer from flux staining and organic residue formation during the solder bump formation process.
Packaging of the ULSI chip is one of the most important steps in ULSI manufacturing, contributing significantly to the overall cost, performance and reliability of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies such as chip bonding have become critical. Packaging of the chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction.
As semiconductor device sizes have decreased, the density of devices on a chip has increased along with the size of the chip thereby making chip bonding more challenging. Packaging of the ULSI chip is one of the most important steps in ULSI manufacturing, contributing significantly to the overall cost, performance and reliability of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies such as chip bonding have become critical. Packaging of the chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction.
One of the major problems leading to package failure as chip sizes increase are problems affecting device materials in high thermal treatment process, for example thermal coefficient of expansion (TCE) mismatches between materials leading to stress buildup and the inability of the device materials to withstand necessary processing temperatures. For example, in flip chip technology chip bonding is accomplished by means of solder bumps formed on under bump metallization (UBM) layers overlying a chip bonding pad where, frequently, high thermal treatments necessary to achieve solder reflow and solder bump formation can lead to damage or undesirable interaction of the solder with adjacent or underlying organic device materials.
Generally solder bump formation includes deposition of a solder material, for example, by physical vapor deposition, electroplating or stencil printing of solder paste into a patterned photoresist stencil pattern. In one approach, a first reflow process is carried out to partially form the solder bump including wetting and forming an adhesion bond with an uppermost underlying metal layer referred to as a wetting layer in a series of metal layers referred to as an under bump metal (UBM) system. The stencil is then removed and a second reflow process is carried out to homogenize and shape the solder bump with the help of surface tension.
In order to form the stencil and define the area over which solder paste will be applied, such as the chip bonding pad, a thick film of photoresist also referred to a dry film resist (DFR) is used to pattern and define an area for depositing the solder paste, for example, by stencil printing. The DFR is then exposed to activating light through a mask to define a pattern overlying the chip bonding pads. Following exposure, the DFR is developed, for example, by a wet chemical process where selected portions of the patterned DFR are removed according to selective dissolution to create a pattern of openings for solder column formation. Following a solder column formation step including, for example, solder paste stencil printing to fill the openings in the patterned DFR, it is necessary to strip (remove) the remaining DFR, for example, by a wet chemical stripping process prior to subsequent processing steps to complete the formation of solder bumps.
It is highly important to completely remove developed portions of the photoresist pattern to avoid problems with subsequent processing steps. In this regard, a reactive ion etch (RIE) cleaning process is frequently performed to ensure removal of the DFR following the photolithographic development process to form the solder column openings. Incomplete removal of the DFR according to a developing procedure or a stripping procedure will lead to subsequent processing defects including improperly formed solder bumps and improperly plasma etched surfaces over the bonding pad.
For example, referring to FIGS. 1Axe2x89xa71E are shown exemplary stages in the solder bump manufacturing process including a cross sectional side view portion of a semiconductor wafer. Shown in FIG. 1A is chip bonding pad 10, for example Cu or Al, formed for example by vapor deposition or electroplating on the upper surface 8 of an underlying multi-level semiconductor device.
Still referring to FIG. 1A, after the chip bonding pad 10 is formed, one or more passivation layers 12 including, for example, a first layer of silicon nitride including an overlying layer of an organic material, for example, polyimide is formed over the semiconductor device surface excluding an area overlying the chip bonding pad 10. Typically, one or more under bump metallization (UBM) layers of from about 500 Angstroms to about 5000 Angstroms is then deposited over chip bonding pad 10 to form a UBM system, e.g., 14A and 14B. Referring to FIG. 1B, a photolithographic patterning and reactive ion etch (RIE) process is performed to etch back the UBM system to reveal the uppermost passivation layer and to leave pre-patterned UBM layers, e.g., 14A and 14B overlying the chip bonding pad. The UBM system including layers 14A and 14B typically includes at least an adhesion layer (e.g., 14A), for example, titanium or aluminum, for adhering to the chip bonding pad and an overlying wetting layer (e.g., 14B), for example copper or nickel, for wetting and forming an adhesion bond with a subsequently formed overlying solder bump.
Referring to FIG. 1C, a layer of dry film photoresist (DFR) 16 is formed over the exposed passivation layer and pre-patterned UBM system and photolithographically patterned to form a solder column opening 16A overlying and encompassing the patterned UBM system, the solder column opening typically being slightly larger in dimension than the UBM system e.g., 14A and 14B. Prior to depositing solder material into solder column opening 16A, for example, by stencil printing solder paste, the bottom portion of the DFR opening including the UBM system and the exposed uppermost passivation layer surface area 16B, are subjected to a plasma (RIE) cleaning process to remove residual DFR. During the plasma cleaning process the exposed passivation layer surface area 16B, is etched thereby reducing the passivation layer thickness and roughening the passivation layer surface area 16B thereby making it more susceptible to subsequent organic residue adhesion and staining.
Referring to FIG. 1D, in a typical approach to forming a solder bump, solder paste is screen printed into the patterned stencil including solder column opening 16A and heated in a first reflow process to form partially formed solder bump 18A as shown. Referring to FIG. 1E, the DFR is then removed by a wet chemical stripping process followed by coating the solder bumps with flux and performing a second reflow process to better homogenize and finalize the shape of the solder bump 18B and to improve adhesion with the wetting layer 14B of the UBM system.
One problem with the prior art solder bump formation process relates to the thermal degradation of the DFR layer following a first reflow process and the interaction of flux contained in the solder material with the roughened passivation layer surface area. For example, referring to FIG. 2 is shown a top planar view of a portion of a semiconductor surface having stained passivation layer surface region e.g., 20 surrounding an exemplary completed solder bump 22. The stained region e.g., 20 is believed to be formed by interaction of both flux and thermally degraded DFR during the first reflow process. Following the second reflow process the stained region including photoresist residue is difficult to remove by conventional wet stripping processes. As a result, the photoresist residue may adversely affect subsequent semiconductor wafer processing steps. For example, the photoresist residue may adversely affect the second reflow process to form the solder ball, for example interfering with proper wetting of the UBM layer, or result in current leakage adversely affecting device functioning. Consequently, semiconductor device quality suffers and die yield is reduced.
There is therefore a need in the semiconductor processing art to develop an improved solder bump formation process whereby solder and photoresist interaction with the semiconductor surface is avoided thereby avoiding residue formation and staining of the semiconductor surface surrounding the solder bumps to improve device quality and die yield.
It is therefore an object of the invention to provide an improved solder bump formation process whereby solder and photoresist interaction with the semiconductor surface is avoided thereby avoiding residue formation and staining of the semiconductor surface surrounding the solder bumps to improve device quality and die yield, while overcoming other shortcomings and limitations of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein the present invention provides a method for protecting a passivation layer during a solder bump formation process.
In a first embodiment, the method includes providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.